1. Field of the Disclosure
The present disclosure relates generally to electronic devices, and more particularly, to data processor devices.
2. Description of the Related Art
Data processor units generally include an instruction execution pipeline that includes various stages that control execution of a current instruction. One stage of the pipeline provides information derived from the current instruction to a load/store unit that accesses a data operand to be used by the instruction based upon the derived information. The derived information is referred to herein as “effective address input operands” because the derived information is used by the load/store unit during an access set-up cycle to calculate an effective address of the instruction operand.
Given sufficient time during the access set-up cycle, the load/store unit will definitively determine the memory where the instruction operand is stored, and will generate an access request that only accesses that memory. However, due to tight timing constraints on the access set-up cycle, it may not be possible during the access set-up cycle to definitively determine which memory stores the instruction operand and generate an access request to access just that memory. Various ways of accommodating this situation include: delaying the generation of an access request by a clock cycle to provide additional access set-up time; generating multiple access requests that are speculative to ensure the instruction operand will be accessed during the access cycle; and generating a single access request that is speculative, and therefore may not be able to access the instruction operand from the target device. Delaying the access request by adding a clock cycle or providing a single access request that is speculative reduces performance of a data processor. Speculatively initiating multiple access requests maintains performance but consumes additional power.